The integration of the semiconductor device has hitherto been achieved mainly by miniaturizing transistors. However, miniaturization of transistors has come to the limit, and when the transistors are attempted to be more miniaturized, there is a risk that the semiconductor device does not operate correctly due to the short-channel effect and the like.
As a method of basically solving this problem, there has been proposed a method of three-dimensionally processing a semiconductor substrate, thereby three-dimensionally forming a transistor. A three-dimensional transistor using a silicon pillar extending perpendicularly to the main surface of the semiconductor substrate as a channel has an advantage in that an occupied area is small and that a large drain current is obtained by a complete depletion. This three-dimensional transistor can be also used for a closest layout of 4F2 (see Japanese Patent Application Laid-open Nos. 2003-303901, H5-136374, H6-209089, H9-8295, and 2002-83945).
In a vertical transistor using a silicon pillar, a gate electrode is positioned on the side surface of the silicon pillar, and a diffusion layer becoming a source or a drain is formed on the upper part of the silicon pillar. Therefore, the gate electrode cannot be easily connected to the upper-layer wiring. For example, there is considered a method of drawing a gate electrode to a flat region of a silicon substrate and connecting a gate contact to this drawing electrode portion. However, according to this method, the gate needs to be patterned by photolithography and etching. Not only the processing process of the gate electrode increases but also a large stage due to the silicon pillar hinders lithography. Therefore, it is extremely difficult to pattern in high precision a gate electrode having a three-dimensional structure.